The present invention relates generally to semiconductor devices, and more specifically, to complementary metal-oxide-semiconductor field-effect transistor (MOSFET or MOS) devices.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS) in which a gate structure is energized to create an electric field that drives electrons through a channel region located between a source region and a drain region of the semiconductor body. CMOS devices have become widely used in the semiconductor industry, wherein both n-type (NMOS) and p-type (PMOS) transistors are used to fabricate logic and other circuitry.
Generally, after a transistor is formed, electrical contacts are made to connect a source region, a drain region, and/or a gate region of the transistor to make the transistor fully functional. Typically, lithographic techniques are used to define contact openings in a dielectric material that surrounds the transistor for the electrical contacts. The contact openings are then filled with a conductive material to form electrical contacts. As device footprints are reduced, increased contact resistance to the source region and the drain region (hereinafter collectively referred to as “source/drain regions”) affects device performance. Silicide liners can be utilized to reduce the contact resistance between the conductive material and the source/drain regions in FETs. For example, nickel platinum (NiPt) silicide liners have proven to improve on-resistance (RON) for p-type devices. When fabricating CMOS devices, silicide liners are not only utilized with the PMOS transistors but are also utilized with the NMOS transistors.